RF Power CMOS

In the mobile wireless industry, system size and cost are important factors for having a competitive product. Because of this, in the future system-on-chip (SOC) solutions are likely to emerge. For wireless communications products, this means that the power amplifier (PA) needs to be integrated with the rest of the analog and digital circuitry. This thesis has experimentally studied the suitability of a commercial 0.25 gm logic CMOS device technology for RF power applications. In particular, the suitability of the standard BSim3v3 device model for accurately capturing RF power behavior has been evaluated. Our study includes DC, small-signal RF, and large-signal RF characteristics. It was found that there are severe discrepancies between the BSim3v3 model and the measured results. A new model was constructed by adding a passive circuit topology that accounts for device parasitics not captured by the BSim3v3 model. The newly developed circuit model has been shown to accurately predict the device's RF power behavior. The physical origins of the new circuit elements and their dependencies on device layout have been identified. Thesis Supervisor: Jesu's A. del Alamo Title: Professor of Electrical Engineering